Default Values

Mythen3

Default values

Name

Value

REQRD_FRMWRE_VRSN

0x230124

KERNEL_DATE_VRSN

Mon May 10 18:00:21 CEST 2021

ID_FILE

detid_mythen3.txt

NUM_HARDWARE_VERSIONS

2

HARDWARE_VERSION_NUMBERS

{0x0, 0x2};

HARDWARE_VERSION_NAMES

{ 1.0, 1.2 }

LINKED_SERVER_NAME

mythen3DetectorServer

CTRL_SRVR_INIT_TIME_US

300 * 1000

NCOUNTERS

3

MAX_COUNTER_MSK

0x7

NCHAN_1_COUNTER

128

NCHAN

128 * NCOUNTERS

NCHIP

10

NCHAN_PER_MODULE

NCHAN * NCHIP

NDAC

16

HV_SOFT_MAX_VOLTAGE

500

HV_HARD_MAX_VOLTAGE

530

HV_DRIVER_FILE_NAME

/etc/devlinks/hvdac

DAC_DRIVER_FILE_NAME

/etc/devlinks/dac

TYPE_FILE_NAME

/etc/devlinks/type

TEMPERATURE_FILE_NAME

/tmp/temp.txt

TEMPERATURE_FILE_NAME

/sys/class/hwmon/hwmon0/temp1_input

DAC_MAX_MV

2048

TYPE_MYTHEN3_MODULE_VAL

93

TYPE_TOLERANCE

5

TYPE_NO_MODULE_STARTING_VAL

800

MAX_EXT_SIGNALS

8

DEFAULT_PATTERN_FILE

DefaultPattern_mythen3.txt

DEFAULT_INTERNAL_GATES

1

DEFAULT_EXTERNAL_GATES

1

DEFAULT_DYNAMIC_RANGE

32

DEFAULT_NUM_FRAMES

1

DEFAULT_NUM_CYCLES

1

DEFAULT_GATE_WIDTH

100 * 1000 * 1000

DEFAULT_GATE_DELAY

0

DEFAULT_PERIOD

2 * 1000 * 1000

DEFAULT_DELAY_AFTER_TRIGGER

0

DEFAULT_HIGH_VOLTAGE

0

DEFAULT_TIMING_MODE

AUTO_TIMING

DEFAULT_SETTINGS

STANDARD

DEFAULT_TRIMBIT_VALUE

0

DEFAULT_COUNTER_DISABLED_VTH_VAL

2800

DEFAULT_READOUT_C0

10

DEFAULT_READOUT_C1

10

DEFAULT_SYSTEM_C0

10

DEFAULT_SYSTEM_C1

6

DEFAULT_SYSTEM_C2

5

DEFAULT_TRIMMING_RUN_CLKDIV

40

DEFAULT_READOUT_C0_STARTUP

20

DEFAULT_ASIC_LATCHING_NUM_PULSES

10

DEFAULT_MSTR_OTPT_P1_NUM_PULSES

20

DEFAULT_ADIF_PIPELINE_VAL

8

DEFAULT_ADIF_ADD_OFST_VAL

0

MAX_TIMESLOT_VAL

0xFFFFFF

IP_HEADER_SIZE

20

FIXED_PLL_FREQUENCY

020000000

READOUT_PLL_VCO_FREQ_HZ

1000000000

SYSTEM_PLL_VCO_FREQ_HZ

1000000000

MAX_NUM_DESERIALIZERS

40

BIT16_MASK

0xFFFF

MAX_TRIMBITS_VALUE

63

NUMSETTINGS

3

NSPECIALDACS

2

SPECIALDACINDEX

{M_VRPREAMP, M_VRSHAPER};

SPECIAL_DEFAULT_STANDARD_DAC_VALS

{ 1100, 1280 }

SPECIAL_DEFAULT_FAST_DAC_VALS

{ 300, 1500 }

SPECIAL_DEFAULT_HIGHGAIN_DAC_VALS

{ 1300, 1100 }

NUM_CLOCKS_TO_SET

3

UDP_IP_HEADER_LENGTH_BYTES

28

PACKETS_PER_FRAME_10G

2

PACKETS_PER_FRAME_1G

20

DACS

Mythen3 DACS

Name

Value

vcassh

1200

vth2

2800

vrshaper

1280

vrshaper_n

2800

vipre_out

1220

vth3

2800

vth1

2800

vicin

800

vcas

1800

vrpreamp

1100

vcal_n

1100

vipre

2624

vishaper

1708

vcal_p

1712

vtrim

2800

vdcsh

800

Gotthard2

Default values

Name

Value

REQRD_FRMWRE_VRSN

0x221123

KERNEL_DATE_VRSN

Mon May 10 18:00:21 CEST 2021

ID_FILE

detid_gotthard2.txt

NUM_HARDWARE_VERSIONS

2

HARDWARE_VERSION_NUMBERS

{0x0, 0x2};

HARDWARE_VERSION_NAMES

{ 1.0, 1.2 }

LINKED_SERVER_NAME

gotthard2DetectorServer

CTRL_SRVR_INIT_TIME_US

300 * 1000

NCHAN

128

NCHIP

10

NDAC

16

NADC

32

ONCHIP_NDAC

7

DYNAMIC_RANGE

16

HV_SOFT_MAX_VOLTAGE

500

HV_HARD_MAX_VOLTAGE

530

HV_DRIVER_FILE_NAME

/etc/devlinks/hvdac

DAC_DRIVER_FILE_NAME

/etc/devlinks/dac

ONCHIP_DAC_DRIVER_FILE_NAME

/etc/devlinks/chipdac

TYPE_FILE_NAME

/etc/devlinks/type

TEMPERATURE_FILE_NAME

/tmp/temp.txt

TEMPERATURE_FILE_NAME

/sys/class/hwmon/hwmon0/temp1_input

CONFIG_FILE

config_gotthard2.txt

DAC_MAX_MV

2048

ONCHIP_DAC_MAX_VAL

0x3FF

ADU_MAX_VAL

0xFFF

ADU_MAX_BITS

12

MAX_FRAMES_IN_BURST_MODE

2720

TYPE_GOTTHARD2_MODULE_VAL

536

TYPE_GOTTHARD2_25UM_MASTER_HD1_V1_VAL

683

TYPE_GOTTHARD2_25UM_SLAVE_HDI_V1_VAL

704

TYPE_GOTTHARD2_25UM_MASTER_HD1_V2_VAL

723

TYPE_GOTTHARD2_25UM_SLAVE_HDI_V2_VAL

747

TYPE_GOTTHARD2_MODULE_VAL

536

TYPE_TOLERANCE

10

TYPE_NO_MODULE_STARTING_VAL

800

INITIAL_STARTUP_WAIT

1 * 1000 * 1000

DEFAULT_BURST_MODE

BURST_INTERNAL

DEFAULT_FILTER_RESISTOR

0

DEFAILT_CDS_GAIN

0

DEFAULT_NUM_FRAMES

1

DEFAULT_NUM_CYCLES

1

DEFAULT_NUM_BURSTS

1

DEFAULT_EXPTIME

0

DEFAULT_PERIOD

0

DEFAULT_DELAY_AFTER_TRIGGER

0

DEFAULT_BURST_PERIOD

0

DEFAULT_HIGH_VOLTAGE

0

DEFAULT_TIMING_MODE

AUTO_TIMING

DEFAULT_SETTINGS

DYNAMICGAIN

DEFAULT_CURRENT_SOURCE

0

DEFAULT_TIMING_SOURCE

TIMING_INTERNAL

DEFAULT_ALGORITHM

ALG_HITS

DEFAULT_READOUT_C0

8

DEFAULT_READOUT_C1

8

DEFAULT_SYSTEM_C0

5

DEFAULT_SYSTEM_C1

10

DEFAULT_SYSTEM_C2

5

DEFAULT_SYSTEM_C3

5

DEFAULT_CNTNS_SYSTEM_C0

10

DEFAULT_CNTNS_SYSTEM_C1

20

DEFAULT_CNTNS_SYSTEM_C2

10

DEFAULT_BURST_SYSTEM_C0

5

DEFAULT_BURST_SYSTEM_C1

10

DEFAULT_BURST_SYSTEM_C2

5

DEFAULT_READOUT_SPEED

G2_108MHZ

SPEED_144_CLKDIV_0

6

SPEED_144_CLKDIV_1

6

SPEED_144_CLKPHASE_DEG_1

122

SPEED_144_DBIT_PIPELINE

1

SPEED_108_CLKDIV_0

8

SPEED_108_CLKDIV_1

8

SPEED_108_CLKPHASE_DEG_1

268

SPEED_108_DBIT_PIPELINE

1

FIXED_PLL_FREQUENCY

20000000

INT_SYSTEM_C0_FREQUENCY

144000000

READOUT_PLL_VCO_FREQ_HZ

866666688

SYSTEM_PLL_VCO_FREQ_HZ

722222224

DEFAULT_CLK1_PHASE_DEG

270

DEFAULT_DBIT_PIPELINE

1

DEFAULT_ASIC_DOUT_RDY_SRC

0x5

DEFAULT_ASIC_DOUT_RDY_DLY

0x3

GAIN_VAL_OFST

12

GAIN_VAL_MSK

0x3 << GAIN_VAL_OFST

VETO_DATA_SIZE

160

BIT16_MASK

0xFFFF

MASTER_NAMES

hardware (master/slave), master, slave

ASIC_ADDR_MAX_BITS

4

ASIC_CURRENT_INJECT_ADDR

0x9

ASIC_VETO_REF_ADDR

0xA

ASIC_CONF_ADC_ADDR

0xB

ASIC_CONF_GLOBAL_SETT

0xC

ASIC_GAIN_MAX_BITS

2

ASIC_GAIN_MSK

0x3

ASIC_G0_VAL

0x0 & ASIC_GAIN_MSK) << ADU_MAX_BITS

ASIC_G1_VAL

0x1 & ASIC_GAIN_MSK) << ADU_MAX_BITS

ASIC_G2_VAL

0x3 & ASIC_GAIN_MSK) << ADU_MAX_BITS

ASIC_CONTINUOUS_MODE_MSK

0x7

ASIC_ADC_MAX_BITS

7

ASIC_ADC_MAX_VAL

0x7F

ASIC_GLOBAL_SETT_MAX_BITS

6

ASIC_EXT_MEMCTRL_OFST

0

ASIC_EXT_MEMCTRL_MSK

0x1 << ASIC_EXT_MEMCTRL_OFST

ASIC_EXT_TIMING_OFST

1

ASIC_EXT_TIMING_MSK

0x1 << ASIC_EXT_TIMING_OFST

ASIC_CONT_MODE_OFST

2

ASIC_CONT_MODE_MSK

0x1 << ASIC_CONT_MODE_OFST

ASIC_FILTER_OFST

3

ASIC_FILTER_MSK

0x3 << ASIC_FILTER_OFST

ASIC_FILTER_MAX_RES_VALUE

3

ASIC_CDS_GAIN_OFST

5

ASIC_CDS_GAIN_MSK

0x1 << ASIC_CDS_GAIN_OFST

IP_HEADER_SIZE

20

UDP_IP_HEADER_LENGTH_BYTES

28

DACS

Gotthard 2 DACS

Name

Value

vref_h_adc

N/A

dac_unused

N/A

vb_comp_fe

N/A

vb_comp_adc

N/A

vcom_cds

N/A

vref_rstore

N/A

vb_opa_1st

N/A

vref_comp_fe

N/A

vcom_adc1

N/A

vref_prech

N/A

vref_l_adc

N/A

vref_cds

N/A

vb_cs

N/A

vb_opa_fd

N/A

dac_unused2

N/A

vcom_adc2

N/A

Moench

Default values

Name

Value

REQRD_FRMWRE_VRSN_BOARD2

0x444445

REQRD_FRMWRE_VRSN

0x231026

NUM_HARDWARE_VERSIONS

2

HARDWARE_VERSION_NUMBERS

{ 0x2, 0x3 }

HARDWARE_VERSION_NAMES

{ 1.0, 2.0 }

ID_FILE

detid_moench.txt

LINKED_SERVER_NAME

moenchDetectorServer

CTRL_SRVR_INIT_TIME_US

300 * 1000

NCHAN

400 * 400

NCHIP

1

NDAC

8

DYNAMIC_RANGE

16

NUM_BYTES_PER_PIXEL

DYNAMIC_RANGE / 8

DATA_BYTES

NCHIP * NCHAN * NUM_BYTES_PER_PIXEL

CLK_RUN

40

ADC_CLK_INDEX

0

DEFAULT_NUM_FRAMES

1

DEFAULT_STARTING_FRAME_NUMBER

1

DEFAULT_NUM_CYCLES

1

DEFAULT_EXPTIME

10 * 1000

DEFAULT_PERIOD

2 * 1000 * 1000

DEFAULT_DELAY

0

DEFAULT_HIGH_VOLTAGE

0

DEFAULT_TIMING_MODE

AUTO_TIMING

DEFAULT_SETTINGS

G4_HIGHGAIN

DEFAULT_TX_UDP_PORT

0x7e9a

DEFAULT_TMP_THRSHLD

65 * 1000

DEFAULT_FLIP_ROWS

0

DEFAULT_SPEED

HALF_SPEED

DEFAULT_PARALLEL_ENABLE

0

HIGHVOLTAGE_MIN

60

HIGHVOLTAGE_MAX

200

DAC_MIN_MV

0

DAC_MAX_MV

2500

MAX_FILTER_CELL_VAL

12

READ_N_ROWS_MULTIPLE

16

MIN_ROWS_PER_READOUT

16

MAX_ROWS_PER_READOUT

400

ROWS_PER_PACKET

8

MAX_TIMESLOT_VAL

0x1F

MAX_THRESHOLD_TEMP_VAL

127999

ASIC_FILTER_MAX_RES_VALUE

1

MAX_SELECT_CHIP10_VAL

63

MAX_PHASE_SHIFTS

200

BIT16_MASK

0xFFFF

ADC_DECMT_QUARTER_SPEED

0x3

ADC_DECMT_HALF_SPEED

0x1

ADC_DECMT_FULL_SPEED

0x0

ADC_PHASE_DEG_QUARTER_SPEED

0

ADC_PHASE_DEG_HALF_SPEED

0

ADC_PHASE_DEG_FULL_SPEED

150

ADC_OFST_QUARTER_SPEED

0x12

ADC_OFST_HALF_SPEED

0x12

ADC_OFST_FULL_SPEED

0x12

ADC_PORT_INVERT_VAL

0x55555555

SAMPLE_ADC_FULL_SPEED

SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL

IP_HEADER_SIZE

20

UDP_IP_HEADER_LENGTH_BYTES

28

MASTER_NAMES

hardware, master, slave

NUMSETTINGS

0

DACS

Moench DACS

Name

Value

vbp_colbuf

1300

vipre

1000

vin_cm

1400

vb_sda

680

vcasc_sfp

1428

vout_cm

1200

vipre_cds

1280

ibias_sfp

900

Ctb

Default values

Name

Value

MIN_REQRD_VRSN_T_RD_API

0x181130

REQRD_FRMWR_VRSN

0x230705

NUM_HARDWARE_VERSIONS

1

HARDWARE_VERSION_NUMBERS

{ 0x3f }

HARDWARE_VERSION_NAMES

{ 5.1 }

LINKED_SERVER_NAME

ctbDetectorServer

CTRL_SRVR_INIT_TIME_US

2 * 1000 * 1000

NCHAN

40

NCHAN_ANALOG

32

NCHAN_DIGITAL

64

NCHAN_TRANSCEIVER

4

NBITS_PER_TRANSCEIVER

64

NCHIP

1

NDAC

24

NPWR

6

NDAC_ONLY

NDAC - NPWR

DYNAMIC_RANGE

16

NUM_BYTES_PER_PIXEL

DYNAMIC_RANGE / 8

CLK_FREQ

156.25

I2C_POWER_VIO_DEVICE_ID

0x40

I2C_POWER_VA_DEVICE_ID

0x41

I2C_POWER_VB_DEVICE_ID

0x42

I2C_POWER_VC_DEVICE_ID

0x43

I2C_POWER_VD_DEVICE_ID

0x44

I2C_SHUNT_RESISTER_OHMS

0.005

DEFAULT_DATA_BYTES

NCHIP * NCHAN * NUM_BITS_PER_PIXEL

DEFAULT_STARTING_FRAME_NUMBER

1

DEFAULT_NUM_SAMPLES

1

DEFAULT_NUM_FRAMES

1

DEFAULT_EXPTIME

0

DEFAULT_NUM_CYCLES

1

DEFAULT_PERIOD

1 * 1000 * 1000

DEFAULT_DELAY

0

DEFAULT_HIGH_VOLTAGE

0

DEFAULT_VLIMIT

-100

DEFAULT_TIMING_MODE

AUTO_TIMING

DEFAULT_TX_UDP_PORT

0x7e9a

DEFAULT_RUN_CLK

200

DEFAULT_ADC_CLK

40

DEFAULT_SYNC_CLK

40

DEFAULT_DBIT_CLK

200

DEFAULT_TRANSCEIVER_MASK

0x3

MAX_TRANSCEIVER_MASK

0xF

UDP_HEADER_MAX_FRAME_VALUE

0xFFFFFFFFFFFF

HIGHVOLTAGE_MIN

60

HIGHVOLTAGE_MAX

200

DAC_MIN_MV

0

DAC_MAX_MV

2500

VCHIP_MIN_MV

1673

VCHIP_MAX_MV

2668

POWER_RGLTR_MIN

636

POWER_RGLTR_MAX

2638

VCHIP_POWER_INCRMNT

200

VIO_MIN_MV

1200

DIGITAL_IO_DELAY_MAXIMUM_PS

OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS

MAX_PHASE_SHIFTS_STEPS

8

WAIT_TME_US_FR_ACQDONE_REG

100

WAIT_TIME_US_PLL

10 * 1000

WAIT_TIME_US_STP_ACQ

100

WAIT_TIME_CONFIGURE_MAC

2 * 1000 * 1000

WAIT_TIME_PATTERN_READ

10

WAIT_TIME_1US_FOR_LOOP_CNT

50

MSB_OF_64_BIT_REG_OFST

32

LSB_OF_64_BIT_REG_OFST

0

BIT32_MSK

0xFFFFFFFF

BIT16_MASK

0xFFFF

MAXIMUM_ADC_CLK

65

PLL_VCO_FREQ_MHZ

800

IP_HEADER_SIZE

20

UDP_IP_HEADER_LENGTH_BYTES

28

Eiger

Default values

Name

Value

LINKED_SERVER_NAME

eigerDetectorServer

NUM_HARDWARE_VERSIONS

2

HARDWARE_VERSION_NUMBERS

{0x0, 0x1};

HARDWARE_VERSION_NAMES

{ FX70T, FX30T }

REQUIRED_FIRMWARE_VERSION

32

ID_FILE

detid_eiger.txt

ID_FILE

detid.txt

CONFIG_FILE

config_eiger.txt

WAIT_STOP_SERVER_START

1 * 1000 * 1000

STATUS_IDLE

0

STATUS_RUNNING

1

STATUS_ERROR

2

ADC_NAMES

FPGA EXT, 10GE, DCDC, SODL, SODR, FPGA, FPGA_FL, FPGA_FR

TOP_NAMES

hardware, top, bottom

MASTER_NAMES

hardware, master, slave

NCHAN

256 * 256

NCHIP

4

NDAC

16

TEN_GIGA_BUFFER_SIZE

4112

ONE_GIGA_BUFFER_SIZE

1040

TEN_GIGA_CONSTANT

4

ONE_GIGA_CONSTANT

16

NORMAL_HIGHVOLTAGE_INPUTPORT

/sys/class/hwmon/hwmon5/device/in0_input

NORMAL_HIGHVOLTAGE_OUTPUTPORT

/sys/class/hwmon/hwmon5/device/out0_output

SPECIAL9M_HIGHVOLTAGE_PORT

/dev/ttyS1

SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE

16

DEFAULT_UDP_SOURCE_PORT

0xE185

DEFAULT_NUM_FRAMES

1

DEFAULT_STARTING_FRAME_NUMBER

1

DEFAULT_NUM_CYCLES

1

DEFAULT_EXPTIME

1E9

DEFAULT_PERIOD

1E9

DEFAULT_DELAY

0

DEFAULT_HIGH_VOLTAGE

0

DEFAULT_SETTINGS

DYNAMICGAIN

DEFAULT_SUBFRAME_EXPOSURE

2621440

DEFAULT_SUBFRAME_DEADTIME

0

DEFAULT_DYNAMIC_RANGE

16

DEFAULT_PARALLEL_MODE

1

DEFAULT_READOUT_OVERFLOW32_MODE

0

DEFAULT_CLK_SPEED

FULL_SPEED

DEFAULT_IO_DELAY

650

DEFAULT_TIMING_MODE

AUTO_TIMING

DEFAULT_PHOTON_ENERGY

-1

DEFAULT_RATE_CORRECTION

0

DEFAULT_EXT_GATING_ENABLE

0

DEFAULT_EXT_GATING_POLARITY

1

DEFAULT_TEST_MODE

0

DEFAULT_HIGH_VOLTAGE

0

MAX_TRIMBITS_VALUE

63

MIN_ROWS_PER_READOUT

1

MAX_ROWS_PER_READOUT

256

MAX_PACKETS_PER_REQUEST

256

UDP_HEADER_MAX_FRAME_VALUE

0xFFFFFFFFFFFF

BIT16_MASK

0xFFFF

BIT32_MSK

0xFFFFFFFF

DAC_MIN_MV

0

DAC_MAX_MV

2048

LTC2620_MIN_VAL

0

LTC2620_MAX_VAL

4095

DAC_MAX_STEPS

4096

MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS

0x1FFFFFFF

SLAVE_HIGH_VOLTAGE_READ_VAL

-999

HIGH_VOLTAGE_TOLERANCE

5

DACS

Eiger DACS

Name

Value

VSvP

0

Vtrim

2480

Vrpreamp

3300

Vrshaper

1400

VSvN

4000

Vtgstv

2556

Vcmp_ll

1000

Vcmp_lr

1000

Vcal

0

Vcmp_rl

1000

rxb_rb

1100

rxb_lb

1100

Vcmp_rr

1000

Vcp

1000

Vcn

2000

Vishaper

1550

Jungfrau

Default values

Name

Value

MIN_REQRD_VRSN_T_RD_API

0x171220

REQRD_FRMWRE_VRSN_BOARD2

0x230920

REQRD_FRMWRE_VRSN

0x230921

NUM_HARDWARE_VERSIONS

2

HARDWARE_VERSION_NUMBERS

{ 0x2, 0x3 }

HARDWARE_VERSION_NAMES

{ 1.0, 2.0 }

ID_FILE

detid_jungfrau.txt

LINKED_SERVER_NAME

jungfrauDetectorServer

CTRL_SRVR_INIT_TIME_US

300 * 1000

NCHAN

256 * 256

NCHIP

8

NDAC

8

DYNAMIC_RANGE

16

NUM_BYTES_PER_PIXEL

DYNAMIC_RANGE / 8

DATA_BYTES

NCHIP * NCHAN * NUM_BYTES_PER_PIXEL

CLK_RUN

40

CLK_SYNC

20

ADC_CLK_INDEX

1

DBIT_CLK_INDEX

0

CONFIG_FILE

config_jungfrau.txt

DEFAULT_NUM_FRAMES

100 * 1000 * 1000

DEFAULT_STARTING_FRAME_NUMBER

1

DEFAULT_NUM_CYCLES

1

DEFAULT_EXPTIME

10 * 1000

DEFAULT_PERIOD

2 * 1000 * 1000

DEFAULT_DELAY

0

DEFAULT_HIGH_VOLTAGE

0

DEFAULT_TIMING_MODE

AUTO_TIMING

DEFAULT_SETTINGS

GAIN0

DEFAULT_GAINMODE

DYNAMIC

DEFAULT_TX_UDP_PORT

0x7e9a

DEFAULT_TMP_THRSHLD

65 * 1000

DEFAULT_NUM_STRG_CLLS

0

DEFAULT_STRG_CLL_STRT

0xf

DEFAULT_STRG_CLL_STRT_CHIP11

0x3

DEFAULT_STRG_CLL_DLY

0

DEFAULT_FLIP_ROWS

0

DEFAULT_FILTER_RESISTOR

1

DEFAULT_FILTER_CELL

0

DEFAULT_PEDESTAL_MODE

0

DEFAULT_PEDESTAL_FRAMES

1

DEFAULT_PEDESTAL_LOOPS

1

HIGHVOLTAGE_MIN

60

HIGHVOLTAGE_MAX

200

DAC_MIN_MV

0

DAC_MAX_MV

2500

MAX_FILTER_CELL_VAL

12

MIN_ROWS_PER_READOUT

8

MAX_ROWS_PER_READOUT

512

READ_N_ROWS_MULTIPLE

8

MAX_TIMESLOT_VAL

0x1F

MAX_THRESHOLD_TEMP_VAL

127999

MAX_STORAGE_CELL_VAL

15

MAX_STORAGE_CELL_CHIP11_VAL

3

MAX_STORAGE_CELL_DLY_NS_VAL

ASIC_CTRL_EXPSRE_TMR_MAX_VAL

ACQ_TIME_MIN_CLOCK

2

ASIC_FILTER_MAX_RES_VALUE

1

MAX_SELECT_CHIP10_VAL

63

MAX_PHASE_SHIFTS

240

BIT16_MASK

0xFFFF

GAIN_VAL_OFST

14

GAIN_VAL_MSK

0x3 << GAIN_VAL_OFST

ADC_PORT_INVERT_VAL

0x5A5A5A5A

ADC_PORT_INVERT_BOARD2_VAL

0x453b2a9c

SAMPLE_ADC_FULL_SPEED_CHIP11

SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_0_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL

SAMPLE_ADC_HALF_SPEED_CHIP11

SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_1_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL

SAMPLE_ADC_QUARTER_SPEED_CHIP11

SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + SAMPLE_DGTL_SAMPLE_2_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL

ADC_PHASE_FULL_SPEED_CHIP11

160

ADC_PHASE_HALF_SPEED_CHIP11

160

ADC_PHASE_QUARTER_SPEED_CHIP11

160

DBIT_PHASE_FULL_SPEED_CHIP11

80

DBIT_PHASE_HALF_SPEED_CHIP11

135

DBIT_PHASE_QUARTER_SPEED_CHIP11

135

ADC_OFST_FULL_SPEED_VAL_CHIP11

0x10

ADC_OFST_HALF_SPEED_VAL_CHIP11

0x08

ADC_OFST_QUARTER_SPEED_VAL_CHIP11

0x04

SAMPLE_ADC_FULL_SPEED_CHIP10

SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_1_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL

SAMPLE_ADC_HALF_SPEED_CHIP10

SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL

SAMPLE_ADC_QUARTER_SPEED_CHIP10

SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL

ADC_PHASE_FULL_SPEED_CHIP10

160

ADC_PHASE_HALF_SPEED_CHIP10

160

ADC_PHASE_QUARTER_SPEED_CHIP10

160

DBIT_PHASE_FULL_SPEED_CHIP10

125

DBIT_PHASE_HALF_SPEED_CHIP10

175

DBIT_PHASE_QUARTER_SPEED_CHIP10

175

ADC_OFST_FULL_SPEED_VAL_CHIP10

0x10

ADC_OFST_HALF_SPEED_VAL_CHIP10

0x08

ADC_OFST_QUARTER_SPEED_VAL_CHIP10

0x04

SAMPLE_ADC_HALF_SPEED_BOARD2

SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL

SAMPLE_ADC_QUARTER_SPEED_BOARD2

SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL

ADC_PHASE_HALF_SPEED_BOARD2

110

ADC_PHASE_QUARTER_SPEED_BOARD2

220

DBIT_PHASE_HALF_SPEED_BOARD2

150

DBIT_PHASE_QUARTER_SPEED_BOARD2

150

ADC_OFST_HALF_SPEED_BOARD2_VAL

0x10

ADC_OFST_QUARTER_SPEED_BOARD2_VAL

0x08

IP_HEADER_SIZE

20

UDP_IP_HEADER_LENGTH_BYTES

28

MASTER_NAMES

hardware, master, slave

NUMSETTINGS

2

NSPECIALDACS

3

SPECIALDACINDEX

{J_VREF_PRECH, J_VREF_DS, J_VREF_COMP};

SPECIAL_DEFAULT_DYNAMIC_GAIN_VALS

{ 1450, 480, 420 }

SPECIAL_DEFAULT_DYNAMICHG0_GAIN_VALS

{ 1550, 450, 620 }

DACS

Jungfrau DACS

Name

Value

vb_comp

1220

vdd_prot

3000

vin_com

1053

vref_prech

1450

vb_pixbuf

750

vb_ds

1000

vref_ds

480

vref_comp

420

Gotthard

Default values

Name

Value

NUM_HARDWARE_VERSIONS

2

HARDWARE_VERSION_NUMBERS

{ 0x1, 0x2 }

HARDWARE_VERSION_NAMES

{ 1.0, 2.0 }

LINKED_SERVER_NAME

gotthardDetectorServer

CTRL_SRVR_INIT_TIME_US

300 * 1000

CONFIG_FILE

config_gotthard.txt

NCHAN

128

NCHIP

10

NDAC

8

NCHIPS_PER_ADC

2

NCHAN_PER_ADC

256

DYNAMIC_RANGE

16

NUM_BITS_PER_PIXEL

DYNAMIC_RANGE / 8

DATA_BYTES

NCHIP * NCHAN * NUM_BITS_PER_PIXEL

CLK_FREQ

32007729

MAX_EXT_SIGNALS

1

IP_PACKET_SIZE_NO_ROI

NCHIP * (NCHAN / 2) * 2 + 14 + 20

IP_PACKET_SIZE_ROI

NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20

UDP_PACKETSIZE_NO_ROI

NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2

UDP_PACKETSIZE_ROI

NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2

DEFAULT_NUM_FRAMES

1

DEFAULT_NUM_CYCLES

1

DEFAULT_EXPTIME

1 * 1000 * 1000

DEFAULT_PERIOD

1 * 1000 * 1000 * 1000

DEFAULT_DELAY

0

DEFAULT_SETTINGS

DYNAMICGAIN

DEFAULT_TIMING_MODE

AUTO_TIMING

DEFAULT_TRIGGER_MODE

TRIGGER_IN_RISING_EDGE

DEFAULT_HIGH_VOLTAGE

0

DEFAULT_PHASE_SHIFT

120

DEFAULT_TX_UDP_PORT

0xE185

DAC_MIN_MV

0

DAC_MAX_MV

2500

DACS

Gotthard DACS

Name

Value

vref_ds

660

vcascn_pb

650

vcascp_pb

1480

vout_cm

1520

vcasc_out

1320

vin_cm

1350

vref_comp

350

ib_testc

2001